The present invention relates generally to integrated circuit (IC) designs, and more particularly to a method for designing phase-lock loop (PLL) circuits.
A PLL circuit is one of the most popular feedback systems for providing closed loop frequency control that can be found in many products such as cell phones, televisions, radio, pagers, computers and other telecommunication devices. The PLL circuit operates based on a phase difference between input and output signals of a controlled oscillator. A typical PLL circuit is composed of a phase detector, a charge pump, a voltage controlled oscillator (VCO), and a loop filter. The phase detector is a nonlinear device that outputs a signal representing a phase difference between two oscillating input signals. The charge pump is a device that converts the phase difference into a current. The VCO is also a nonlinear device whose oscillation frequency is controlled by a low voltage input signal. The loop filter is a low-pass filter (LPF) that is necessary in order for the PLL circuit to function properly.
The PLL circuit is not simple in design. An IC manufacturer typically provides its customers with a set of already verified PLL intellectual property (IP). The term IP refers to the data representing a circuit design to be implemented on a semiconductor substrate. Conventionally, the PLL IP is generally designed for satisfying a broad range of applications. While the generally-designed PLL IP may be used to provide a clock source that operates properly for its required task, its circuit performance is less than optimal. Furthermore, such PLL circuit usually occupies an undesirably large layout area.
One solution to the above-mentioned issues is to have the PLL circuit customarily designed in order to improve its area utilization and performance. However, the customized designs are expensive and time-consuming. Furthermore, the equipment used for supporting the customized designs usually requires a lot of maintenance. Since each customized PLL circuit is unique, the PLL IP resulted therefrom cannot be flexibly used in designing other PLL circuits.
Thus, it is desirable to have an improved service model for IC manufacturers that provides the customers with the PLL IP, which can be flexibly used for a broad range of applications, without compromising on their circuit performance and area utilization.